module andgate (a,b,c);
input a,b;
output c;
and gat(c,a,b);
endmodule;
Showing posts with label VLSI. Show all posts
Showing posts with label VLSI. Show all posts
Saturday, 17 December 2011
Micro Wind Verilog Code for And Gate
module andgate (a,b,c);
input a,b;
output c;
and gat(c,a,b);
endmodule;
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